1. Field of the Intention
The present invention generally relates to providing tailored implants for semiconductor devices and, more particularly, to utilizing disposable spacers to define the region of source/drain and extension implants.
2. Background Description
The size of dynamic random access memory (DRAM) chips is expected to reach 64 GBits per chip in the year 2010. By then the gate_length of the metal_oxide_semiconductor (MOS) transistors that make up such a chip is expected to be approximately 70 nm. There are several benefits to the reduction of feature size and the attendant increase in circuit density. At the circuit performance level, there is an increase in circuit speed. With shorter distances to travel and with the individual devices occupying less space, information can be put into and gotten out of a chip in less time. These same density improvements can also result in a chip that requires less power to operate. Also, making the individual chip components smaller and closer together, along with creating a larger chip, yields faster and more powerful circuits.
For scalable DRAM and logic technologies beyond 0.15 :m minimum feature size, a separate tailoring of impurity implants of the different devices used on the same chip is needed to control device characteristics and undesirable effects are encountered in extremely small devices. For example, as gate dimensions shrink, the gate leakage current due to short_channel effects becomes an ever_increasing issue. The control of short_channel effects in metal oxide semiconductor field effect transistors (MOSFETs) is one of the biggest challenges in scaling to subxe2x80x940.1 micron dimensions. In the ideal case, a MOSFET should behave like a switch, i.e. the device current drive should be high when the device is on, and there should be minimal leakage in the device when the device is off As device dimensions are reduced, it becomes very difficult to maintain this ideal switching behavior of complementary metal oxide semiconductor (CMOS) transistors. The primary impact of the short_channel effect is to increase the leakage or off_current when the devices are in the off_state. To scale devices into the subxe2x80x940.1 micron dimensions, there have been significant efforts devoted to the aggressive design of the dopant profiles within the device.
In larger devices, it has been the practice to control dopant profile at the ends of the conduction channel adjacent to the source and drain regions. This practice has been extended to sub-lithographic dimensions by the use of insulative spacers (generally oxide) which are formed on the sides of the gate structure. That is, after the gate structure is formed, a first impurity implant is performed self-aligned with the gate structure, a sidewall spacer is formed on the sides of the gate structure and another impurity implantation process is performed self-aligned with the sidewalls. This process can be repeated to develop more complex impurity concentration profiles. However, the sidewall spacers which are built up during this process cannot be removed and must, in the context of preferred CMOS technology, generally be applied to both the NFET and PFET of a complementary transistor pair. Since the conduction characteristics of these devices are very different and the transistors generally formed at different sizes to obtain similar current conduction, the conduction characteristics cannot be simultaneously optimized for both types of transistor on a single chip.
For example, to avoid hot carrier effects, a particular type of short channel effect, several techniques have been proposed. One of these techniques is lightly doped drain extension regions, or xe2x80x9cLDDxe2x80x9d regions. In this structure, a first light and shallow implant is performed before sidewall spacers are formed on the gate structure. Sidewall spacers are conventionally used as an aid to source/drain profiling, since they provide a self-aligned sublithographic pattern modification. After the sidewall spacers are in place, a second heavier implant is performed. The first implant provides only a relatively low conductivity in the silicon, but this prevents the channel_drain voltage difference from appearing entirely at the drain boundary. By increasing the distance over which this voltage difference occurs, the peak electric field is reduced, and this tends to reduce channel hot carrier (CHC) effects. The doses needed for LDD regions have now become closer to those used for the main source/drain implant, and therefore LDD regions are often referred to as xe2x80x9cMDDxe2x80x9d (medium_doped drain) regions.
In addition to reducing undesirable device operational characteristics, there also exists a need to provide a fabrication method that can provide tailored spacer thicknesses for P-FETs (p-type field effect transistor) and N_FETs (n-type field effect transistor). By providing different spacer thicknesses for P-FETs and N-FETs, the distance between source, drain and gate regions for each type device could be tailored independently, which can advantageously be used to control, for example, the diffusion constant between P-FETs and N-FETs. However, separate and independent tailoring of NFET and PFET devices cannot be achieved using conventional built-up spacers without extreme process complexity and criticality (such as multiple implant block out masking processes) and attendant compromise of manufacturing yield.
Additionally, extremely high integration density in, for example, DRAM arrays implies a need to form structures having equal line and space dimensions at the minimum lithographic feature size, referred to as xe2x80x9con pitchxe2x80x9d. An on pitch DRAM array and other on pitch devices cannot tolerate wider spacers (e.g. approaching one-half the minimum feature size or greater) which might be required for support junctions. That is, since conventional built-up spacers cannot be removed, a spacer width of one-half the minimum feature size would completely close the structure and preclude the formation of contacts. Insufficient space for contacts may result from even somewhat narrower spacers in devices formed at extremely high integration density.
It is therefore an object of the invention to provide a method for tailoring source and drain implants of different devices used on the same chip in order to minimize the region of overlap of the source and drain regions into the gate region.
It is another object of the invention to provide a method for tailoring impurity implants of the different devices.
It is yet another object of the invention to provide a method that enables different spacer thicknesses for P-FETs and N-FETs to be fabricated independently.
It is a further object of the invention to provide a reduction in process complexity for manufacture of CMOS integrated circuits by avoidance of at least one implant block out mask process.
In the preferred embodiment, the method involves applying a block out mask over a first gate structure. The mask is exposed, and a layer of spacer material, preferably a polymer, is deposited over the block out mask and a second gate structure adjacent to the block out mask. Preferably, a reactive ion etch (RIE) is performed to form spacers, from the spacer material, along the side of the block out mask material and second gate structure. A source/drain (S/D) implant is then applied in the region defined by the spacers. An additional isotropic etch is used to reduce the spacer thickness. The reduced spacer thicknesses defines the region for extension implants. This process, in accordance with the invention reverses the order of the source/drain and extension implants and avoids one block out masking process for each reduction in spacer thickness. Standard resist and polymer material strip process are then performed to take off and dispose of the block out mask and spacers.